1. Field of the Invention
The present invention relates to a routing analysis method, a logic synthesis method and a circuit partitioning method for an integrated circuit.
2. Description of the Background Art
The present routing analysis method for an integrated circuit is a method for calculating a routing difficulty index which indicates difficulty in routing in a case where routes are placed in a layout region of the integrated circuit, from a netlist which is information on cells constituting the integrated circuit and connection of the cells. As a conventional method for calculating the routing difficulty index from the netlist, a method of calculating the number of nets and the number of connections between terminals, or calculating a ratio of the number of nets and the number of connections between terminals to the number of cells has been proposed.
The general routing analysis method or the like is disclosed in, for example, Japanese Patent Application Laid Open Gazette No. 10-116915 (Patent Document 1).
The routing difficulty index obtained from the netlist, conventionally, indicates the number of nets and the number of connections between terminals, or a ratio of the number of nets and the number of connections between terminals to the number of cells. Even if the number of nets and the number of connections between terminals are large in the netlist, however, there is a case where the difficulty in an actual routing is low since the length of a route which is placed shorter than a predicted route length. Therefore, the conventional routing difficulty index has a problem of low accuracy of prediction.